TSV Multiplexing: A 3D NoC Occupancy Analysis

Networks-on-chip (NoCs) are proposed as promising packet-based communication platforms for multi-processor system-on-chip (MPSoC) design, due to scalability, better throughput and reduced power consumption [1]. NoC-based architectures are characterized by various trade-offs with regard to structural characteristics, performance specifications, and application demands. However, increasing the number of cores over a 2D plane is not efficient due to long network diameter and overall communication distance. In this context, with the emergence of viable 3D integration technology [2], opportunities exist for chip architecture innovations.